Apparatus for deriving information signals for component television video signal reception

ABSTRACT

Receiving apparatus for receiving multiplexed analogue component signals each of which represents a line of a television picture and includes a burst of digital signals, at least one of the multiplexed analogue component signals including at a predetermined location within its digital burst an indication of further information, the apparatus comprising a demodulating device for demodulating received multiplexed analogue component signals, means responsive to the output of the demodulating device for synchronizing the receiving apparatus to the received multiplexed analogue component signals, and a data extraction circuit responsive to the synchronizing means for extracting from the demodulated signals the indication of further information and for controlling the operation of the demodulating device in accordance with the further information.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a system for transmitting and/orreceiving television video signals in component form, which componentshave been time compressed and placed sequentially so as to occupy,together with the necessary sync and clamping signals, a periodsubstantially identical to the existing line period e.g. approximately64 μS.

2. Prior Art

It has already been proposed to compress the video component signals tosuch an extent that an audio signal can be included either before orafter the video component signal, within the line period. It ispreferred that this audio signal takes the form of a digital signalplaced before the video components signal. Further, it has been proposedto add to this digital signal a predetermined sequence of digits for useas either a sound or line sync signal.

SUMMARY OF THE INVENTION

We propose that one or more of said predetermined digital sequences canbe replaced, preferably by a further digital sequence, in order tosignal additional information to a receiver.

The present invention provides receiving apparatus for receivingmultiplexed analogue component signals each of which represents a lineof a television picture and includes a burst of digital signals, atleast one of the multiplexed analogue component signals including at apredetermined location within its digital burst an indication of furtherinformation, the apparatus comprising a demodulating device fordemodulating received multiplexed analogue component signals, meansresponsive to the output of the demodulating device for synchronisingthe receiving apparatus to the received multiplexed analogue componentsignals, and a data extraction circuit responsive to the synchronisingmeans for extracting from the demodulated signals the indication offurther information and for controlling the operation of thedemodulating device in accordance with the further information.

BRIEF DESCRIPTION OF THE DRAWINGS

In order that the present invention be more readily understood,reference will now be made to the accompanying drawings, in which:

FIG. 1 shows diagrammatically a multiplexed component signal showing thetime division multiplex between the component parts thereof;

FIG. 2 shows diagrammatically a frame of C-MAC signals offset by 1/2frame and 1/2 line as well as the multiplex timing of each line in theframe.

FIG. 3 shows a block diagram of a receiver incorporating the presentinvention;

FIG. 4 shows a more detailed block diagram of a part of the receivershown in FIG. 3;

FIG. 5 shows a state diagram to explain the operation of the circuitshown in FIG. 4;

FIG. 6 shows a more detailed block diagram of modification to the blockdiagram shown in FIG. 4; and

FIGS. 7A and 7B show state diagrams to explain the operation of thecircuit shown in FIG. 6.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

The Multiplex Analogue Components (MAC) system for whom televisionsignal transmission replaces the colour subcarrier coding of NTSC, PALand SECAM with a single method of time compression. The conventionalstudio colour coder is replaced by a MAC coder which separately timecompresses each active picture line (52 μs nominally) of luminance (Y)and chrominance (alternate lines contain U and V). By using eithercharge-coupled devices (ie CCDs) or digital storage, these compressedluminance and chrominance components can be placed in sequence withinthe 64 μs of each line period. Conventional sync pulses, designed forreceiver technology of 30 years ago, are no longer required and arereplaced by other synchronisation information within the waveform. Thecolour subcarrier burst is no longer required, and any timinginformation required for future developments such as extended definitionreceivers can be derived from the video and sound/data signals.

This time compression results in a proportionate increase in thebandwidth required to pass the signal. The extra bandwidth of thetime-compressed baseband signal can be accommodated within a satelliteFM transmission channel, since the spectral width of the FM signal is afunction of both the frequency and amplitude of the baseband signals.

In one version of MAC known as C-MAC, the synchronisation, sound anddata signals are digitally modulated onto the carrier in theline-blanking interval of the MAC signal, giving an overall timedivision multiplex of the RF carrier as shown in FIG. 1. The completeabsence of high frequency sub-carriers either for colour or for soundallows the bandwidth of the baseband signals to be increased with theupper limit set by interference constraints. The use of large amounts ofpre- and de-emphasis to reduce distortion on subcarriers becomesunnecessary. As a result, the pre- and de-emphasis can be reduced to alevel to give optimum noise and interference performance.

Time division multiplexing of the digital synchronisation, sound anddata with the analogue video signal is carried out at an intermediatefrequency, switching between digital modulation for the synchronisation,sound and data, and frequency modulation for the chrominance andluminance as shown in FIG. 1. Such switching is carried out withoutdiscontinuity of phase in the main carrier.

The internationally agreed studio standard for component-coded digitalvideo has been established with sampling frequencies 13.5 MHz forluminance and 6.75 MHz for chrominance. Luminance compression of 1.5:1and chrominance compression of 3:1 which are used for C-MAC mean thatafter compression the effective sampling frequencies for both luminanceand chrominance are 20.25 MHz. For convenience of generation andrecovery, the same data rate is chosen for the sound signal.

In defining the waveform, it is convenient to divide the 64 usec videoline into 1296 time slots or `samples` based on integer periods of 49.4nsec (1/20.25 MHz) which are shown in FIG. 2 which shows the format of aC-MAC signal offset by 1/2 line and 1/2 frame.

On this basis, the line is broken into the three component parts of thetime division multiplex as shown in Table I.

                  TABLE I                                                         ______________________________________                                        Number of bits/samples                                                                      Total duration Function                                         ______________________________________                                        8      bits       0.40 μsec   digital                                                                       synchron-                                                                     isation                                      186    bits       9.18 μsec   digital                                                                       sound/data                                   1102   samples    54.42 μsec  analogue                                                                      video(MAC)                                   ______________________________________                                    

Referring to FIGS. 1 and 2, a line of multiplexed analogue componentstelevision signal comprises a first portion (a) which contains signalsdigitally modulated on to the R.F. carrier in the line blanking intervalof the signal. The R.F. carrier is preferably modulated using a form ofphase-shift keying shown as 2-4PSK. Following the first portion (a) is asecond portion (b) which contains the chrominance and luminancecomponent signals and which is modulated in a different way e.g.frequency modulated.

As shown in FIG. 2, the portion (a) is further divided into asynchronising section and a sound and/or data section.

It is possible to consider the line as made up of a fixed number ofequal intervals and the positions of the boundaries of the intervals maybe defined by a number. We contemplate using one specific modulationsystem e.g. 2-4PSK to encode a section of the position (a) so as toconstitute what we will call a "unique word". The section used for the"unique word" is in the same position in each line in which it ispresent. The "unique word" is used to convey information about thestructure of the remainder of the signal and particularly enablerecovery of the positions of the boundaries referred to above.

The information recovered may be by virtue of the presence or absence ofa "unique word" at a predetermined vertical location, and/or by virtueof the bit sequence of the word. The following information may beconveyed:

(1) type of modulation system used between each boundary;

(2) type of service or signal conveyed by the modulation describedabove;

(3) line and frame synchronisation for vision signal, if carried;

(4) encryption key for some or all of the services; or

(5) any other data to be carried outside of the services themselves.

Using the above system, it is possible to provide video signalsindicative of function of different aspect ratio by using a "uniqueword" to alter the boundaries of the chrominance and luminanceinformation sections. This may mean that the length of the sound/datasection has to be reduced and that the compression ratio of the videocomponents has to be altered. Another option would be to use certainlines in the field blanking interval to convey further information. The"unique word" signals one of these to the receiver.

Turning now to FIG. 3, there is shown in block diagram terms, a part ofa television receiver. A television signal such as that shown in FIG. 1is received and fed to a demodulator 1 where the digital portion of thesignal is demodulated. The output from the demodulator is fed to a linesequence recognition circuit 2, to a frame sequence recognition circuit3, and to a data extraction circuit 4. The line and frame sequencerecognition circuits produce video line and frame synchronising pulsesfor use by the rest of the receiver circuitry (not shown) as well asproviding synchronisation signals to the data extractor circuit 4. Thedata extraction circuit 4 may be gated by line count from the frame syncso as to be operable only at times when a "unique word" is to beexpected. This will reduce the number of errors.

Within the data, there may be a encryption key and this is output, ifpresent, from the data extraction circuit 4. Otherwise, the dataextraction circuit may be used to look for and decode one or more"unique words" and the control information deriver therefrom is fed toother circuitry. In this embodiment, it is contemplated that anadditional demodulator 6 may be provided and this or the principaldemodulator, under the control of the information from the data`extraction circuit 4` will produce signals indicative of visioninformation, sound information, or other information or a combination ofthese.

It will be appreciated that two types of demodulation are required withthe above-described MAC signal, one type for the digital portion of thesignal and a different type for the vision portion of the signal. The"unique word" can be used to control the demodulating circuit 6 byindicating to the demodulating circuit 6 when to commence and/or stopdemodulation of one of the two types of demodulation whereby to enable areceiving apparatus to receive additional sound and/or vision signalsoutside the usual position determined by the MAC signal described inrelation to FIG. 1.

From the above, it will be appreciated that it is necessary to acquireand lock on to the transmitted sync signals before being in a positionto extract the "unique words". We will therefore describe howsynchronisation of a receiver may be achieved.

Synchronisation signals for C-MAC are:

(i) video line sync

(ii) video frame sync

(iii) U/V identification

(iv) Extended-definition synchronisation

(v) Sound synchronisation

(i) Video line sync: This is available in two ways:

(a) From the digital burst. The first 8 bits of the digital burst carrysynchronisation information, consisting of a run-in bit for differentialdetection and seven bits for the synchronising words. There are two linesynchronising words W₁ and W₂ which are sent on alternate lines. Theirrelative positions are inverted once every frame to provide a framereference as shown in Table 2 below.

                  TABLE 2                                                         ______________________________________                                        Frame  Line     Sync     Frame  Line   Sync                                   Number Number   Word     Number Number Word                                   ______________________________________                                        even   620      W.sub.2  odd    620    W.sub.1                                       621      W.sub.1         621    W.sub.2                                       622      W.sub.2         622    W.sub.1                                       623      W.sub.1         623    W.sub.2                                       624      W.sub.2         624    W.sub.1                                       625      W.sub.2         625    W.sub.1                                Frame Boundary                                                                odd     1       W.sub.1  even    1     W.sub.2                                        2       W.sub.1          2     W.sub.2                                        3       W.sub.2          3     W.sub.1                                        4       W.sub.1          4     W.sub.2                                        5       W.sub.2          5     W.sub.1                                       etc      etc             etc    etc                                    ______________________________________                                    

The two line sync words are defined as:

W₁ =1 0001101

W₂ =0 1110010

Unique words. On 20 lines of each frame, one of the line sync words e.g.the word is replaced with a 7 bit word which may be used for signallingpurposes.

These lines are as follows:

Even frames--line 26, 58, 74, 90, 152, 182, 198, 216, 276, 308, 324,340, 400, 432, 458, 466, 526, 558, 574, 590.

Odd frames--line 27, 59, 75, 91, 153, 183, 199, 217, 277, 309, 325, 341,401, 433, 459, 467, 527, 559, 575, 591.

Even and odd frames are defined in Table 2.

Line syncs may also be derived by detecting a unique frame sync wordplaced in line 625 as shown in FIG. 2 and using this to lock anoscillator running at line rate.

(b) From the video waveform. This is provided by the exact spacing ofedges `e` and `h` of FIG. (2). Edges which may occur in pictures at thesame spacing are eliminated by the field sync lines in which there is nopicture information. The amplitude of the sync edges (0.5 v) allows forrugged sync separation.

(ii) Video field sync: This is available in two ways:

(a) From the digital burst. The first 8 bits of the digital burstprovide not only the line syncs, but by inversion of the relativepositions of the words once every frame a rugged frame sync is providedas shown in Table 2 above. Alternatively, a distinct and unique fieldsync word can be inserted in line 625 as shown in FIG. 2.

(b) From the video waveform. Line 1 of the video and line 313 provide avery rugged method of frame synchronisation, since these lines aredistinguishable from any other line of each frame. The waveform of line1 corresponds to Y=-0.15 and U=-0.65, while that of line 313 correspondsto Y=-1.15 and U=+0.65 (V=0, ie these are lines of U chrominance). Thesevalues are outside the permitted RGB limits for picture information.Frame sync separation, field identification, line count and indeed linesync can be established from these lines.

(iii) U/V identification. The U/V identification is derived directly byline count from the frame sync derived in `b` above. The odd lines ofthe frame carry U information and the even lines carry V information.

(iv) Extended definition synchronisation. For extended processing whichmay be introduced in the future, the 20.25 MHz clock required isrecovered form the sound data burst.

(v) Sound synchronisation. Sound synchronisation is obtained byobtaining line and frame synchronisation from the digital burst whichthen provides total synchronisation of the sound/data channel.

Turning now to the generation of sync signals at the receiver from theC-MAC waveform shown in FIG. 1, it will be recalled that the timings forthe MAC receiver are derived from a line-locked 20.25 MHz clock. Thishas a period of ≈49 nS, and there are 1296 clock samples per televisionline. As timing information for clock regeneration is derived from thedata burst, it can be seen that timing information is only present for15% of the time.

The synchronisation period consists of an 8-bit sequence transmitted atthe start of each data burst. Of this the first bit is a run-in bit, andwithout synchronisation detection can be considered to be of no usefulvalue. The other seven bits contain both the horizontal and verticalsync information in the format shown below.

From Table 2 it will be appreciated that a line sync can be consideredto consist of either the word pair W₁ W₂ or the pair W₂ W₁.

A frame sync will then consist of the sequences W₁ W₁ W₂ W₂ or W₂ W₂ W₁W₁ reversing a W₁ W₂ pair at the frame boundary.

The choice of words for W₁, W₂ is governed solely by the desiredbehaviour of the system under conditions of noise.

Both W₁ and W₂ should be chosen to have smallest possible correlationwith shifted versions of themselves to prevent false lock occuring.

Based on computer search, the seven bit sequence 0001101 has been foundto be optimum with regard to shifted versions of itself and alsosimulation of the sequence by video/data and noise.

In order to prevent confusion between W₁ and W₂ occurring in thereciever, a large Hamming distance between the two is desirable, andhence W₂ was chosen to be 1110010.

To keep the average D.C. level to 1/2, the run in bit was chosen to be 1for W₁ and 0 for W₂.

Receiver Sync Detection

Although only seven bits of sync information are sent on each line, thesequence of W₁ W₂ allows an effective line sync word length of 14 bitsand an effective frame sync word length of 28 bits to be used. This isshown below:

    ______________________________________                                              Sync                    Frame Sync                                      Line  Word   Line Sync Sequence                                                                             Sequence                                        ______________________________________                                         n     W.sub.1                                                                                   W.sub.1 W.sub.2                                            n + 1 W.sub.2                W.sub.2 W.sub.1                                   n + 2                                                                               W.sub.1                                                                                   W.sub.1 W.sub.2                                            n + 3 W.sub.2                W.sub.2 W.sub.2 *                                 n + 4                                                                               W.sub.2                          W.sub.2 W.sub.2 W.sub.1 W.sub.1                          W.sub.2 W.sub.1.sup.!                                                                              (or W.sub.1 W.sub.1                   n + 5 W.sub.1                W.sub.1 W.sub.1 *                                                                        W.sub.2 W.sub.2)                       n + 6                                                                               W.sub.1                                                                                   W.sub.1 W.sub.2                                            n +  7                                                                              W.sub.2                W.sub.2 W.sub.1                                   n + 8                                                                               W.sub.1                                                                                   W.sub.1 W.sub.2                                            n + 9 W.sub.2                                                                 ______________________________________                                    

A line sync is therefore present on every line and a frame sync once aframe.

On the lines marked * a line sync is not detected due to the W₁ W₂ pairinversion to signal a frame sync. The ability of the system to stay inlock is not affected because the line sync detection is inhibited duringthese 2 lines once a frame lock is established.

The line marked ! contains a valid line sync, but the W₁ W₂ pairsequence is inverted. This can be used as a less rugged form of framesync if desired for a simpler receiver and is indicated in FIG. 2.

A block diagram of the receiver detector is shown below in FIG. 4, and abrief description of the operation follows.

A phase locked loop (not shown) recovers the 20.25 MHz clock from theincoming data stream in a conventional manner. Even when not locked, theoscilllator of the phase locked loop is running at a nominal 20.25 MHzand so there is only scale difference in phase between the incoming datastream and the oscillator which results in long period of in phaserunning of the oscillator to facilitate lock-up.

The input serial data stream is then converted to an n bit wide paralleldata stream by a serial to parallel converter 20, where n is the widthof the line sync (ie n=7).

This is processed by a sync word recognition circuit 21 which convertsthe continuous 20 Mb/s data sream to a continuous error pattern. Thatis, the output represents the number of bits that the input is away fromW₁. For example, in the case of W₂ this is the Hamming distance, or 7.

Line Sync Extraction

Since ρ_(W).sbsb.1 =ρ_(W).sbsb.2, by inverting the present sample andsumming this with the same sample from the previous line, a maximum willoccur with the line pair W₁ W₂ and a minimum with the pair W₂ W₁. Bycomparing these with ρ_(a).sbsb.min and ρ_(a).sbsb.max (the number oferrors allowed in a sync word pair before a detection is deemed to bemissed) line syncs may be extracted (along with other false detectionsdue to random data) from the input data stream.

The figure ρ_(l) may be used as a measure of the BER for the channel.

This operation is achieved by means of an inverter 22 which inverts thepresent sample and feeds it to one input of an adder 23 whose otherinput is supplied with the output from a line delay circuit 24. Theoutput of the adder 23 is fed to a comparing circuit 25 where the 4 bitoutput of the adder 23 is compared with predetermined maximum andminimum numbers of errors and if the level of the output of the adder 23falls between the maximum and minimum numbers of errors a line syncdetection signal is generated.

A frame sync signal could also be extracted from the circuit 25 bydetection when minimum and maximum signals are produced.

Frame Sync Extraction

This is preferably performed in a manner similar to line syncs with oneimportant difference. The uninverted present sample is in this casesummed with the same sample from the previous line in an adder 27. Thisgives a minimum for W₁ W₁ and a maximum for the sequence W₂ W₂. Thisresult is delayed by two lines in a delay circuit 28 which comprises a2×4 bit 2 line gated latch and added to the inverted undelayed signal inan adder 30.

Again this result has a minimum for W₂ W₂ W₁ W₁ and a maximum for W₁ W₁W₂ W₂. By using a comparison circuit 31 for comparing this result withthe number of errors allowable before a detection is not signalled,frame syncs may be detected.

The significant difference between frame sync and line sync extractionis the two line delay circuit 28. This is simply a two element shiftregister clocked with the regenerated line sync.

Once line lock has been established, the precise horizontal position ofthe frame sync within one of only 625 possible positions. It iseffectively `pointed to` by the line syncs. Hence the frame sync is mademuch more robust. This contrasts with a system using a frame sync wordonly ie where the frame sync may be in one of 625×1296 locations.

Acquisition of Lock

The previous section described in the recovery of the sync pulses. Falsesync pulses may also be generated by the random data in the channel, orby a particular arrangement of video signals. Therefore some sort ofdiscrimination is required to extract the true syncs from any possiblemisdetections.

The process by which lock is acquired is governed by the state diagramshown in FIG. 5.

In the initial state any detection of the sync word is accepted, and acounter connected to the output of the comparing circuit 25 is moved tostate ○2 .

If this detection is not the sync word then the counter returns to state○1 .

If it is the sync word, the counter progresses to state ○4 and thesystem has aquired lock.

Once line syncs have been acquired, the position of the data burst isknown with certainty, and the clock recovery PLL is gated to preventspurious signals (eg video) outside the burst increasing the amount ofjitter on the clock.

After 16 consecutive mis-detections the system reverts to state ○1 andhas lost lock.

The state diagram is the same for line and frame syncs, but acquisitionof frame sync is not initiated until line lock is acquired when theposition of frame sync can be indicated by line syncs.

The figures in this diagram allow lock to be acquired and held at a C/Nof 0 dB in the UKIBA C-MAC system. This has been confirmed byexperimental results.

Sync acquisition is thus by two distinct processes:

(1) Detection of line and frame sync.

(2) Lock acquisition and digital flywheeling.

Clock recovery is gated as soon as line lock is established (3 lines)thereby reducing clock jitter at low C/N. The clock has only to runungated for 3 lines as opposed to running ungated accurately for atleast one frame.

FIG. 6 shows a block diagram of a part of a receiver concentrating onsync detection and acquisition which differs from that shown in FIG. 4in that it is much more simple and easy to instruct.

The previously described receiver required a fairly substantial amountof hardware, mostly running at the 20.25 Mb/s clock rate.

The receiver shown in FIG. 6 and described below has a considerablyreduced amount of logic running at 20.25 MHz and in particular containsno line store. The same reference numerals are used for the same partsas in FIG. 4.

In FIG. 6, serial incoming data is inverted as before in a circuit 40 toproduce a 3-bit error word. A line sync acquisition and flywheel andstate counter circuit 41 receives an input from a word detection circuiteach time a W₁ or W₂ word is detected by a word detection circuit 42connected to the output of the circuit 40. It also receives the linesync detection signal generated by the comparing circuit 25. The countercircuit 41 generates a number of outputs among which is a line rateclock signal which is fed to a 3-bit latch 43 which replaces the linedelay circuit 24 of FIG. 4.

The counter circuit 41 also acts as a reference signal generator forgenerating reference signals for application to a word detector andadaptive error control circuit 44, the reference signal being used toselect the type of detection and number of errors tolerated by thedetector 42 and the comparing circuit 25.

For frame sync detection, the arrangement is as described in relation toFIG. 4 with the 2 line delay 28 responsive to the line rate clock nowgenerated by the counter circuit 41. Adaptive error control is achievedusing a frame sync flywheel and acquisition circuit 46 and an errorcontrol circuit 47 which operates in a similar manner to thecorresponding circuits described in relation to line sync detector.

The process of line sync acquisition will now be described withreference to FIG. 6 and FIGS. 7A and 7B.

Initially search for W₁ (only W₁ detections are output from a comparatoron the output of the serial to error converter 40, allowing n errors).

If W₁ is found, the counter circuit 41 moves to state 1 (FIG. 7A) andsearches for an occurrence of W₂ precisely 1296 clock cycles (1 line)later. This is also output form the word recognition circuit 42 since W₁=W₂.

If W₂ is not found, the counter circuit 41 reverts to state 0 (FIG. 7A)and continues to search for another occurrence of W₁.

If W₂ is found, then the probability of having found a line sync pair isquite high, and the receiver switches over to the sum of errors mode ofthe previous receiver, except that in this case, the line store isreplaced by 3-bit latch 43 clocked by the assumed position of line syncfound from the separate W₁ and W₂ detections.

The counter circuit 41 is now at state 2 in (FIG. 7A).

If the syncs were correctly indentified then the conventional lockingprocedure will be followed and the counter circuit 41 will sit at state5 (in FIG. 7A) and the receiver will have acquired line lock and a linesync output will be generated by the circuit 41.

At this point, the search for frame lock is initiated and when framesync is acquired a frame sync output is generated from the circuit 46.

Frame syncs are detected using a 2 latch double line delay as before,and frame lock is also acquired as before.

In both line and frame cases, increasing BER will increase theprobability of sync detection being missed and hence the counters 41 and46 will advance from the in lock state. After a number of counts fromthese states (n_(l) and n_(F)) the number of errors tolerated before async word detection is missed is increased using the circuits 44 and 47,therefore giving a greater probability of detecting a sync word in thepresence of noise. Once a word is detected and the system returns to thein lock state, the number of errors tolerated is reduced to the originallevel.

Once frame lock is lost, re-acquisition takes place as normal.

Once line lock is lost, instead of reverting to state zero, the countercircuit 41 reverts to state 2.

There are two reasons for loss of line lock--loss of signal, or mconsecutive mis-detections due to noise.

In the former case the counter circuit 41 will return to state 0 viastate 2.

In the latter case, if sync words are detected there is the possibilityof re-acquiring lock whilst still running in the two word mode therebyconsiderably reducing the interruption to sound the vision caused byloss of lock.

Adaptive error tolerance on either or both line and frame syncdetection, allows sync extraction in the presence of a greater amount ofnoise (or higher BER). The arrangement shown in FIG. 6 has an increasedinitial lock up time with respect to that of FIG. 4. This is increasedby an average of 11/2 lines in low BER conditions to approximately 40lines at a BER of 10⁻¹.

Although not shown in FIG. 3, it will be appreciated that a modifiedversion of the counter circuit 41 in FIG. 6 will be used and thatadaptive error control of the circuit 25 and/or circuit 31 is possible.

We claim:
 1. Apparatus for receiving a television signal comprising timemultiplexed analog video components and digital signals representinglines of at least one television frame, the television signal includingsynchronization information and in the digital signals of at least oneof the lines of each television frame, at a predetermined position inthe multiplex, an indication of further information, the receivingapparatus comprising;a demodulating device for demodulating at leastpart of the received television signal; a synchronization circuitresponsive to an output of the demodulating device for the acquisitionof synchronization information from the demodulated signal; and a dataextraction circuit responsive to the synchronization circuit forextracting the indication of further information from the predeterminedposition in the demodulated signals, for the production of the furtherinformation from the indication of further information and forcontrolling the demodulating device to operate further on the receivedsignal in one of a plurality of predetermined modes in accordance withthe further information whereby to recover the component signals fromthe multiplex.
 2. Apparatus according to claim 1, wherein thedemodulating device comprises a first demodulator for demodulating thedigital signals and a further demodulator controlled by the dataextraction circuit for demodulating the analog video component signals.3. Apparatus according to claim 1, wherein the indication of furtherinformation is in the form of a digital word at a predetermined locationin the digital signals of a predetermined one of the lines of eachtelevision frame, and the data extraction means detects said digitalword.
 4. Apparatus according to claim 2, wherein the indication offurther information is in the form of a digital word at a predeterminedlocation in the digital signals of a predetermined one of the lines ofeach television frame and the data extraction means detects said digitalword.
 5. Apparatus according to claim 3, wherein the data extractionmeans controls operation of the demodulating device to alter theboundary between the digital signals and the multiplexed analog videocomponents constituting the remainder of the line.
 6. Apparatusaccording to claim 4, wherein the data extraction means controlsoperation of the demodulating device and the further demodulating deviceto alter the boundary between the digital signals and the multiplexedanalog video components constituting the remainder of the line. 7.Apparatus according to claim 4, wherein the data extraction circuitcontrols operation of the demodulating device and the furtherdemodulating device to alter the period of the demodulation of theanalog video component portion of the multiplex of digital signals andanalog component signals.
 8. Apparatus according to claim 3, wherein thedata extraction circuit controls operation of the demodulating device toalter the period of the demodulation of the analog video componentportion of the multiplex of digital signals and analog video componentsignals.
 9. Apparatus for receiving a television signal comprising timemultiplexed analog video components and digital signals representinglines of at least one television frame, the television signal includingsynchronization information and in the digital signals of at least oneof the lines of each television frame at a predetermined position in themultiplex, an indication of further information, the receiving apparatuscomprising;a demodulating device for demodulating at least part of thereceived television signals; a synchronization circuit responsive to anoutput of the demodulating device for the acquisition of synchronizationinformation from the demodulated signal; and a data extraction circuitresponsive to the synchronization circuit for extracting of theindication of further information from the predetermined position in thedemodulated signal for the production of the further information fromthe indication of further information, for controlling the demodulatingdevice to operate further on the received signal in one of a pluralityof predetermined modes according to the further information to recoverthe component signals from the multiplex, and for controlling theoperation of the receiving apparatus for the subsequent processing ofthe demodulated analog video component signals in accordance with thefurther information.